Technical Field
The present disclosure relates to converters and, more particularly, to a control device for quasi-resonant AC/DC off-line converters.
Description of the Related Art
Converters, and particularly offline drivers of LED-based lamps for bulb replacement, are often desired to have a power factor greater than 0.9, low total harmonic distortion (THD) and to provide safety isolation. At the same time, for cost reasons, it is desirable to regulate the output DC current required for proper LED driving without closing a feedback loop.
High-power-factor (hi-PF) flyback converters are able to meet power factor and isolation specifications with a simple and inexpensive power stage. In a hi-PF flyback converter there is not an energy reservoir capacitor directly connected across the DC side of the input rectifier bridge, so that the voltage applied to the power stage is a rectified sinusoid. To achieve high-PF, the input current must track the input voltage, thus originating a time-dependent input-to-output power flow. As a result, the output current contains a large AC component at twice the main line's frequency.
A quasi-resonant flyback converter has the power switch turn-on synchronized to the instant the transformer demagnetizes (i.e. the secondary current has become zero), normally after an appropriate delay. This allows the turn-on to occur on the valley of the drain voltage ringing that follows the demagnetization, often termed “valley-switching.” Most commonly, peak current mode control is used, so the turn-off of the power switch is determined by the current sense signal reaching the value programmed by the control loop that regulates the output voltage or current.
In a flyback converter the input current is the average of the primary current, which flows only during the ON-time of the power switch, resulting in a series of triangles separated by voids corresponding to the OFF-time of the power switch. This “chopping” causes the average value of the primary current to be lower than half the peak value and depend on the mark-space ratio of the triangles. As a result, the input current is no longer proportional to the envelope of the peaks and unlike the envelope, which is sinusoidal, the input current is not sinusoidal. Although a sinusoidal-like shape is maintained, the input current is distorted. This distorted sinusoidal input current results in a flyback converter that fails to achieve low THD or unity power factor.
FIG. 1 shows a schematic of a high power factor (Hi-PF) quasi resonant (QR) flyback converter 30 according to the prior art. On the primary side, the flyback converter 30 comprises a bridge rectifier 34 having inputs 32, configured to receive an AC voltage from an AC power line, a first output connected to ground, and a second output at which the rectifier is configured to produce a rectified voltage Vin(θ). The converter 30 also includes a capacitor Cin, which serves as a high-frequency smoothing filter, connected across the output terminals of the bridge rectifier 34, with a negative terminal connected to ground. A primary winding Lp of a transformer 36 has one end connected to the positive terminal of the capacitor Cin and the transformer 36 also includes an auxiliary winding Laux coupled to a resistor RZCD. The other end of the primary winding Lp is connected to the drain of a power switch M. The power switch M has a source terminal connected to ground via a sensing resistor Rs, the resistor RS allowing reading of the current flowing through M (i.e. the current flowing through Lp when M is ON) as a positive voltage drop across the resistor Rs itself. A controller 38 controls the power switch M. The primary side of the converter also includes a resistive voltage divider, made up of resistors Ra and Rb connected in parallel with the capacitor Cin, and a clamp circuit 39 that clamps the spikes on the drain voltage due to the leakage inductance of the primary winding Lp.
On the secondary side of the converter, a secondary winding Ls of the transformer 36 has one end connected to the secondary ground and the other end connected to the anode of a diode D having a cathode connected to the positive plate of a capacitor Cout that has its negative plate connected to the secondary ground. This flyback converter 30 generates at its output terminals across Cout a DC voltage Vout that will supply a load (not shown). The load is generally a string of high-brightness LEDs.
The quantity to be regulated (either the output voltage Vout or the output current Iout) is compared to a reference value and an error signal IFB depending on their difference is generated. This signal is transferred to the primary side by an isolated feedback block 40, typically implemented by an optocoupler (or other means able to cross the isolation barrier complying with the safety requirements of IEC60950). On the primary side, this error signal is a current IFB that is sunk from a dedicated pin FB in the controller 38, producing a control voltage Vc on said pin FB. If the open-loop bandwidth of the overall control loop, determined by a frequency compensation network located inside the isolated feedback block 40, is narrow enough—typically below 20 Hz—and a steady-state operation is assumed, the control voltage Vc can be regarded as a DC level, at least to a first approximation.
Inside the controller 38, control voltage Vc is internally fed into one input of a multiplier block 42, having another input that receives, via a pin MULT and a midpoint of the resistive divider Ra/Rb a portion of the instantaneous rectified line voltage Vin(θ) sensed across Cin.
The output of the multiplier block 42 is the product of a rectified sinusoid times a DC level, then still a rectified sinusoid whose amplitude depends on the rms line voltage Vin(θ) and the amplitude of the control voltage Vc; this will be the reference voltage VcsREF(θ) for the peak primary current.
The VcsREF(θ) signal is fed to the inverting input of a pulse width modulation comparator 44 that receives at its non-inverting input the voltage Vcs(t, θ), sensed across the sense resistor Rs, which is a voltage proportional to the instantaneous current Ip(t, θ) flowing through the primary winding Lp of the transformer 36 and the power switch M when the power switch is ON. Assuming power switch M is initially ON, the current through the primary winding Lp will be ramping up and so will the voltage across Rs. When Vcs(t, θ) equals VcsREF(θ) the PWM comparator 44 resets a SR flip-flop 46, which switches off the power switch M. Therefore, the output of the multiplier 42, shaped as a rectified sinusoid, determines the peak value of the current in the primary winding Lp that, as a result, will be enveloped by a rectified sinusoid.
When the power switch M is switched off, the energy stored in the primary winding Lp is transferred by magnetic coupling to the secondary winding Ls and then dumped into the output capacitor Cout and the load until the secondary winding Ls is completely demagnetized. At this point, the diode D opens and the drain node, which was fixed at Vin(θ)+VR while the secondary winding Ls and the diode D were conducting, becomes floating. The drain node voltage would tend to eventually reach the instantaneous line voltage Vin(θ) through a damped ringing due to its parasitic capacitance that starts resonating with the primary winding Lp. The quick drain voltage fall that follows transformer 36 demagnetizing is coupled to a pin ZCD of the controller 38 through the auxiliary winding Laux and the resistor RZCD. A zero-crossing detector (ZCD) block 48 releases a pulse every time it detects a negative-going edge falling below a threshold and this pulse sets the SR flip flop 46 and drives ON the power switch M, starting a new switching cycle.
An OR gate 50 between the ZCD block 48 and the set input of the SR flip flop 46 allows the output of a starter block 52 to initiate a switching cycle. The starter block 52 produces a signal at power-on when no signal is available on the pin ZCD input and prevents the converter 30 from getting stuck in case the signal on the pin ZCD input is lost for any reason.
Assuming θϵ(0, π), according to the control scheme under consideration the peak envelope of the primary current is given by:Ipkp(θ)=Ip(TON,θ)=IPKp sin θ.
It is worth noticing that this scheme results in a constant ON-time TON of the power switch M:
      T    ON    =                    L        p            ⁢                                    I            PKp                    ⁢          sin          ⁢                                          ⁢          θ                                      V            PK                    ⁢          sin          ⁢                                          ⁢          θ                      =          Lp      ⁢                        I          PKp                          V          PK                    
For simplicity, the OFF-time TOFF(θ) of the power switch M will be considered coincident with the time TFW(θ) during which current circulates on the secondary side. In other words, the time interval TR during which the voltage across the primary switch rings until reaching the valley of the ringing will be neglected. This is acceptable as long as TR<<TOFF(θ).
The switching period T(θ) is therefore given by:T(θ)=TON+TFW(θ).
Considering volt-second balance across the primary winding Lp it is possible to write:
            T      FW        ⁡          (      θ      )        =            t      ON        ⁢                                        V            PK                    ⁢          sin          ⁢                                          ⁢          θ                          V          R                    .      
where VR is the reflected voltage, i.e. the output voltage Vout times the primary-to-secondary turns ratio n=Np/Ns, seen across the primary winding Lp of the transformer 36 in the time interval TFW(θ):VR=n(Vout+VF)
wherein VF is the forward drop on the secondary diode D. Therefore, T(θ) can be rewritten as:T(θ)=TON(1+Kv sin θ)
with Kc=VPK VR.
The input current to the converter 30 is found by averaging the primary current Ip(t,θ) in the primary winding Lp over a switching cycle. Ip(t,θ) is the series of gray triangles in the right-hand side diagram of FIG. 2 so it is found that:
                                          I            in                    ⁡                      (            θ            )                          =                                            1              2                        ⁢                                          I                pkp                            ⁡                              (                θ                )                                      ⁢                                          T                ON                                            T                ⁡                                  (                  θ                  )                                                              =                                    1              2                        ⁢                          I              PKp                        ⁢                                                            sin                  ⁢                                                                          ⁢                  θ                                                  1                  +                                                            K                      v                                        ⁢                    sin                    ⁢                                                                                  ⁢                    θ                                                              .                                                          (        1        )            
This shows that the input current is not a pure sinusoid. The function sin θ/(1+Kv sin θ), plotted in FIG. 3a for different values of Kv, is a periodic even function, at twice the line frequency. Conversely, the current drawn from the mains will be its “odd counterpart,” at the line frequency, as shown in FIG. 3b. 
This current is sinusoidal only for Kv=0; when Kv≠0, although a sinusoidal-like shape is maintained, the input current is distorted, the higher Kv the higher the distortion. Since Kv cannot be zero (which would require the reflected voltage to tend to infinity), this prior art QR control scheme does not permit zero total harmonic distortion (THD) of the input current nor unity power factor in the flyback converter 30 even in the ideal case.
FIG. 4, shows the plots of the THD of the input current and of the Power Factor vs. Kv for the converter 30 of FIG. 1.
Although the distortion is significant, especially at high line (i.e. high Kv), the individual harmonics are still well within the limits considered by the regulation on the limits for harmonic current emissions, the IEC61000-3-2 (or its Japanese homologous, the JEIDA-MITI). An example of harmonic measurements on a real-world application is shown in FIG. 5. For this reason the Hi-PF QR flyback converter is currently widely used, especially in solid stating lighting (SSL) applications where safety isolation from the power line is required by regulations. These include LED drivers from few watts to few ten watts for residential and professional lighting.
Still considering the SSL market, recently this inherent distortion is becoming a problem. In fact, as shown in the plot of FIG. 4, it is difficult to meet the target THD<10% (or even lower) that is becoming a market specification in some geographical areas. Low values of Kv should be used even at high line, which means a high reflected voltage VR; since the power MOSFET in a flyback converter should be rated for a breakdown voltage significantly larger than VPKmax+VR, in principle a high VR is provided using a high voltage rating MOSFET, which is more expensive and has higher parasitic losses. In practice, the target VR might be so high that a MOSFET with adequate voltage rating could be prohibitive in terms of cost or originate too much power loss, or even be unavailable.